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Laker 3.2v3p6
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  • 更新时间:2010-03-28 19:36:20
  • 软件类别:国外软件 / 电子电路
  • 软件语言:英文
  • 授权方式:商业版
  • 联系方式:ygqh@21cn.com
  • 官方主页:Home Page
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  • 运行环境:Linux

软件简介

Laker 3.2v3p6

Silicon Canvas的Laker系列产品作为业界技术领先的全定制版图设计解决方案,已经为众多IC设计公司,晶圆厂,LCD供应商和设计服务公司采用。

关于Silicon Canvas,Inc.

Silicon Canvas于2001年在美国加利福利亚州由Hau-yung Chen博士和其它业界资深人士积累超过50年的定制版图设计和设计自动化经验创立,其目标是提供新一代全定制版图设计解决方案,显著提高设计效率,减少产品上市时间。

Silicon Canvas致力于模拟电路,混合信号电路,大规模IC,ASIC和SoC设计市场,其主要产品Laker全定制集成电路版图设计系统是一个可控的全定制版图设计自动化解决方案,它使过去低效率的全定制版图设计过程得到设计质量和自动化操作的平衡。Laker不但可应用于模拟,混合信号,test key的设计,也可为复杂的ASIC和SoC提供时序收敛的修正,顶层模块集成,顶层绕线等应手段,将传统设计效率提高达2-6倍。作为成熟的产品化工具,其业界领先的技术优势已为全球1000多个产品验证,包含高性能CPU,嵌入式控制器,计算机系统,网络,多媒体,图像处理和通讯等领域。

关于Laker系列全定制版图设计系统

Laker全定制集成电路版图设计系统是一个可控的全定制版图设计自动化解决方案,它使过去低效率的全定制版图设计过程得到设计质量和自动化操作的平衡。Laker可以显著提高设计效率达2-6倍,其业界领先的技术优势已为全球1000多个产品验证,适用于大中小各种规模,数字/模拟/数模混合,亚微米和深亚微米,全定制集成电路版图设计。

技术领先地位:

1. 业界唯一可靠的Schematic Driven Layout版图设计解决方案

2. 领先的版图器件模型Magic Cell

3. 开放的集成环境可无缝嵌入各种设计流程

4. 业界最快的版图文件读写速度和处理超大文件的能力

5. 支持深亚微米设计规则

产品特点:

1. 支持电路图和版图对应互操作

2. 提供飞线,自动版图复用,短路检查器,半自动和全自动绕线等工具帮助快速完成复杂互连。

3. 支持读取CDL,EDIF网表,LEF/DEF,ASCII,GDS文件,并可直接操作Open Access,Milkyway以及Volcano库文件,无需数据格式变换过程。

4. 内建Stick Diagram,Matching Editor,Automatic Transistor Placer,Custom Floor Planner等多种工具辅助实现布局优化。

5. Magic Cell支持自动产生可灵活操作的器件版图,确保没有设计规则错误。

6. 内建实时设计规则检查器和实时互连检查器,将DRC和LVS错误可能降到最小。

7. 具备版图纠错功能,并可与第三方物理验证工具结合,迅速查找和自动修正DRC/LVS错误。

8. 支持业界所有主要半导体加工厂的工艺

9. 支持TCL/TK工业标准语言扩展

::::::English Description::::::

Major Benefits Cuts layout time in half while sustaining important aspects of handcrafted layout density Total system allows user to create layout from floor planning, device creation, placement, wire connection, to layout verification and correction without the need for data translation Supports latest process design rules to meet the physical implementation requirements of Ultra-Deep-Submicron (UDSM) and Design-For-Manufacturing (DFM) Fully customizable bind keys to increase individual productivity and reduce the learning curve for new users Device-level manipulation reduces tedious/error-prone layout creation and editing. Shape and Grid Based routers for both full custom and cell-based design applications Download foundry-certified Laker technology files to instantly use the plug-and-play Laker solution Schematic-Driven Layout Flow works efficiently with legacy and new designs Major Features Integration Capability Versatile System: Import designs from EDIF, Spice netlist, or work with Laker-AMS to perform Schematic-Driven Layout flow. Integration with 3rd party physical verification solutions: Tight link with Mentor Graphics Calibre and Synopsys Hercules for DRC/LVS. Run Calibre or Hercules on one block or the whole chip directly from the Laker menu. Layout Planning Custom Floor Planner: Supports block area estimation with reshaped aspect ratio. Assigns pin locations automatically and provides congestion map information to offer best-practice floor planning scheme. Mixes Soft and Hard Instances to minimize the gap between top-down planning and bottom-up layout realization. Stick Diagram Compiler: Provides a higher level of abstraction enabling more efficient transistor floorplanning, such as gate merging, swapping and splitting. Automatic Transistor Placer: Optimum transistor placement achieved automatically through chaining, folding, and connectivity-based placement. Matching Creator: Customize transistor symmetry using a high level abstraction matching table. Quickly realize transistor placement according to user-defined matching patterns. Advanced Device Model Magic Cell (MCell): Built-in UDSM DRC-correct device generator. Provides flexible device models thus enabling extremely efficient creation of the devices physical layout from circuit components of a netlist or schematic. Magic Cell reduces the effort for device preparation and provides higher levels of device manipulation. Most importantly, Magic Cell is the only device model that has the ability to deliver handcrafted quality and guarantee zero DRC violations. Built-in Shape and Grid Based Router Net Router: Automatically route single or multiple nets, DRC and LVS clean. Point to Point Router: Click on source and target to automatically create a DRC clean route. Or use it in an interactive mode while routing between source and target. Interactive settings for each layer include (1) availability for routing, (2) horizontal and vertical cost functions, and (3) width and space. Pathfinder: Interactive single layer DRC-correct path creator. Router follows the mouse in a point and click mode, recognizing same layers and routing around them. Use bind keys to switch between routing layers. Route by Label: Using text, or labels, as a guide, routes are automatically created between multiple points. Hierarchy Manipulation Capability Manipulate circuit hierarchy on Design Browser or Layout Window in order to optimize layout. Pattern Recognition Technology Copy & Associate: Automatically comb through design database to find matches for selected items. Then automatically copy physical layouts and assign correct connectivity. Drastically reduce time spent on building repeat circuitry. Pattern Reuse: Automatically comb through design database to find matches for cells where the hierarchy of the physical layout does not match that of the original schematic. Copy patterns and create new layouts with correct connectivity. Drastically reduce time spent on building repeat circuitry. Correct-by-Construction Rule-Driven Editing: While editing polygons, automatically check, display, and snap to width, space, notch, overlap, and enclosure rules. Increases productivity by reducing need to use rulers and look up design rules. Flight Lines & Real-Time Short Detector: Flight Lines guide user on where to wire. Real-Time short detector displays short errors as they are created. Both are used to ensure LVS-correct layout results. Push Wire: Create a path where you want, push-wire will move same layer routes out of the way. ECO Capability Laker compares an ECO netlist with the existing layout and then displays physical and/or logical discrepancies in the Design Browser window. Use automated functions to fix the discrepancies and match the layout back to the schematic. Layout Debugging and Correction Auto DRC Correction: Fix DRC violations automatically, based on user selected area or Laker DRC error viewer. All fixed layout results will keep original connections, so as not to introduce additional LVS violations. Supports Laker-iDRC, Calibre, and Hercules DRC verification tool error reports. Hierarchical Net Tracer: Provides a unique feature to trace physical net connectivity through any/all levels of hierarchy. Verification Explorer: Seamless integration with third-party industry standard layout verification tools allows the user to browse and debug DRC errors.

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